The present invention relates to insulated gate thyristors used as power switching devices.
Thyristors have been used due to their low on-voltage characteristics as indispensable devices for large capacity power conversion. Gate turn-off ("GTO") thyristors are used very often in the high-voltage, large-current range. However, drawbacks of the GTO thyristors have also become apparent. The drawbacks include: (1) GTO thyristors have a small turn-off gain and require a large gate current for turn-off; (2) GTO thyristors require large snubber circuits for safely turning off the thyristors; (3) the switching speed of the GTO is low, which limits its use to the low frequency range.
In 1984, V. A. K. Temple (cf. IEEE IEDM Tech. Dig., 1984, p282) disclosed a MOS control thyristor ("MCT") which may be classified as a voltage-driven type thyristor. Since then, analysis and improvement of the MCT have been done world wide. This is because the MCT is a voltage driven type thyristor which can be driven with a much simpler gate circuit than the GTO thyristors, and since the MCT turns on at low on-voltage. Recently, new device structures have been proposed which have two insulated gate structures and operate in a thyristor mode when the devices are turned on and at an IGBT (Insulated Gate Bipolar Transistor) mode when the devices are turned off (cf. S. Momota et al., Proc. of IEEE ISPSD, '92(1992), p28, and Y. Seki et al., Proc. of IEEE ISPSD, '93(1993), p159). The new devices realize the low on-voltage characteristics and the high speed switching characteristics in one single device by switching between the operation modes.
FIG. 10 is a sectional view of a double insulated gate MOS device disclosed in 1992 (hereinafter referred to as "DGMOS"). In FIG. 10, a unit (hereinafter referred to as "cell") which includes two control electrodes is shown. An active region which performs switching operation for the conduction and interruption of the main current of the DGMOS is comprised of very many cells. Though the DGMOS includes a voltage withstand structure for sharing the withstand voltage in the peripheral region which surrounds the active region, the description of the voltage withstand structure, which is not related to the essential part of the present invention, will be omitted.
In FIG. 10, an (n) type base layer 43 is formed on an (n) type buffer layer 42 laminated on a surface of a (p) type collector layer 41. A (p) type base region 44 is selectively formed in a surface layer of the (n) type base layer 43. And, (n) type emitter regions 45 are selectively formed in a surface layer of the (p) type base region 44. Emitter regions 46 of (p) type are selectively formed in a surface layer of each (n) type emitter region 45. An emitter electrode 55, connected to an emitter terminal E, contacts in common to the (p) type emitter regions 46 and the (n) type emitter region 45. The first gate electrode 51 is disposed on the first gate oxide film 48 above a surface area of the (n) type emitter region 45 sandwiched between the (p) type base region 44 and the (p) type emitter region 46 and to an exposed surface of the (n) type base layer 43. The first gate electrode 51 is covered with an insulation film 57 and connected to the first gate terminal G1. The second gate electrode 52 is disposed on the second gate oxide film 54 above a surface area of the (n) type emitter region 45 sandwiched between the (p) type emitter region 46 and the (p) type base region 44 and to an exposed surface of the (p) type base region 44. The second gate electrode 52 is covered with the insulation film 57 and connected to the second gate terminal G2. A collector electrode 53, connected to a collector terminal C, contacts to a back surface of the (p) type collector layer 41.
To control the DGMOS, a voltage, the wave form of which is shown in FIG. 11, is applied to the first and second gate electrodes. When the voltage exceeds a threshold value, an inversion layer is formed in the surface area of the (p) type base region 44 below the first gate electrode 51. As electrons pass through the inversion layer, an electron current flows into the (n) type base layer 43 and the (n) type buffer layer 42. Since a positive voltage is applied to the collector electrode 53, the current which has flowed into the (n) type base layer 43 and the (n) type buffer layer 42 yields a base current of a built in pnp transistor consisting of the (p) type collector layer 41, the (n) type buffer layer 42 and the (n) type base layer 43, and the (p) type base region 44. The base current modulates the conductivity of the (n) type base layer 43 and switches on the pnp transistor. A hole current caused by the conductivity modulation yields a base current of a built in npn transistor consisting of the (n) type buffer layer 42 and the (n) type base layer 43, the (p) type base region 44, and the (n) type emitter layer 45, and drives the npn transistor. Since a pnpn transistor consisting of the (p) type collector layer 41, the (n) type buffer layer 42 and the (n) type base layer 43, the (p) type base region 44, and the (n) type emitter layer 45 finally operates, the DGMOS is turned on by the application of the positive voltage to the terminal G1.
The DGMOS of FIG. 10 is turned off by switching off the gate voltages applied to the gate electrodes 51 and 52 with a time lag as shown in FIG. 11. The voltage of the second gate electrode 52 grounded at time t1 becomes negative with respect to the voltage of the emitter electrode 53. As a result, an inversion layer is formed in the surface layer of the (n) type emitter region 45 below the second gate electrode 52, and a p-channel MOSFET is switched on. Since the switching-on of the p-channel MOSFET causes a short circuit of the (p) type base region 44 and the (n) type emitter region 45, the basic structure becomes equivalent to an IGBT. Thus, the DGMOS usually operates in the thyristor mode through the first gate electrode 51, and shifts to the on-state of the IGBT operation mode at the time t1 at the start of turn-off in response to negatively biasing the second gate electrode 52 with respect to the first gate electrode 51. At the time t2, 3 to 4 .mu.sec after the IGBT operation mode started, the DGMOS is turned off by switching off the voltage applied to the first gate electrode 51 to stop the electron supply.
The double insulated gate MOS thyristor disclosed in 1993 has lowered its on-resistance by converting the p-channel device of FIG. 10 to an n-channel one. These devices have features of mode switching which realizes in one single device the low on-resistance of the thyristor and the high speed switching of the IGBT.
However, since a large tail current is caused in the MCTs, they, like the GTO thyristors, are used only in the low frequency range. Furthermore, the maximum controllable current of the double insulated gate thyristors is so small that practical use of the double insulated gate thyristors is limited.